1. Field of the Invention
The present invention relates to a package for accommodating electronic parts intended for inhibiting the variation of characteristic impedance of signal lines, electrical coupling between signal lines, crosstalk noise, and ground bounce, and to a method for manufacturing semiconductor devices and packages.
2. Description of Related Art
FIG. 4 is a sectional view of a semiconductor device illustrating an example of conventional semiconductor devices, and FIG. 5 is a plan of the semiconductor device shown in FIG. 4. In FIG. 4, 1 is a semiconductor chip, 2 is a buildup substrate, 3 is a stiffener, 4 is a first adhesive, 5 is a second adhesive, 6 is a heat spreader, 7 is a solder ball, 8 is a bump, 9 is an under-fill resin, and 10 is a heat conducting resin. Referring to FIGS. 4 and 5, a conventional semiconductor device has a ball-grid-array structure (case-type BGA), in which a semiconductor chip 1 is installed on a buildup substrate 2 composed of an organic material through a bump 8 as FIG. 4 shows, then the vicinity of the bottom of the semiconductor chip 1 is fixed to the central portion of the buildup substrate 2 using an under-fill resin 9 (see FIG. 5), the semiconductor chip 1 is sealed together with a metal stiffener 3 and a heat spreader 6 with a first adhesive 4 and a second adhesive 5, and bumps 8 and solder balls 7 are attached.
FIG. 6 is an enlarged sectional view of the semiconductor device of FIG. 4, and FIG. 7 is a pattern diagram of the semiconductor device of FIG. 4. In FIG. 6, 11 is a signal line, 12 is a ground plane, 13 is a core through hole, 14 is a buildup via, 15 is a core insulating layer, 16 is a first core interconnecting layer, 17 is a second core interconnecting layer, 18 is a first buildup insulating layer, 19 is a second buildup insulating layer, 20 is a first buildup interconnecting layer, 21 is a second buildup interconnecting layer, 22 is a first solder resist, 23 is a second solder resist, 24 is the thickness of the first adhesive, 25 is the thickness of the first solder resist, and 26 is the thickness of the first buildup insulating layer. Referring to FIGS. 6 and 7, the buildup substrate 2 comprises core insulating members such as the core insulating layer 15; core conductor layers such as the core through hole 13, the first core interconnecting layer 16, and the second core interconnecting layer 17 (see FIG. 7); buildup insulating layers such as the first buildup insulating layer 18, (having the thickness 26), and the second buildup insulating layer 19; buildup conductor layers in which the buildup via 14, the first buildup interconnecting layer 20, and the second buildup interconnecting layer 21 are densely formed (see FIG. 7); solder resists such as the first solder resist 22 (having the thickness 25) and the second solder resist 23; and a solder resist opening. The first solder resist 22 is adhered to the stiffener with the first adhesive 4 (having the thickness 24), and the ground plane 12 is mainly formed on the core conductor layer and the pattern of the signal line 11 is mainly formed on the buildup conductor layer.
However, in a conventional case-type BGA structure using a buildup substrate 2 of a 4-layer structure, the ground plane 12 has a pattern having a large opening due to the through-holes of core layer (core through-hole 13), and the following problems in electrical properties arise. The first problem is that the variation of characteristic impedance of interconnections is large when the interconnection lies on the ground plane 12, and when the interconnection lies on the through hole of the core layer (core through hole 13). The second problem is that crosstalk noise is increased especially when the interconnection lies on the through hole of the core layer (core through hole 13). The third problem is that since the pattern of the ground plane 12 has a large opening, the inductance of the ground plane 12 is increases, resulting in a large ground bounce.
In order to solve the above-described problems, the object of the present invention is to provide a package for accommodating electronic parts intended for inhibiting the variation of characteristic impedance of signal lines, electrical coupling between signal lines, crosstalk noise, and ground bounce, and to a method for manufacturing semiconductor devices and packages.
According to a first aspect of the present invention, there is provided a package for accommodating electronic parts, comprising: a structure, wherein a buildup substrate having a power source and/or a ground layer formed on a core substrate, and signal lines formed on a buildup interconnecting layer is adhered to a stiffener with a conductive adhesive layer using a conductive adhesive, and a grounding plane is formed using the stiffener and the buildup substrate.
According to a second aspect of the present invention, there is provided a semiconductor device, comprising: a grid-array structure, wherein a buildup substrate having a power source and/or a ground layer formed on a core substrate, and signal lines formed on a buildup interconnecting layer is adhered to a stiffener with a conductive adhesive layer using a conductive adhesive, and a grounding plane is formed using the stiffener and the buildup substrate, after a semiconductor chip has been installed on the buildup substrate through a bump, the vicinity of the bottom of the semiconductor chip is fixed on the central portion of the buildup substrate with under-fill resin, the semiconductor chip is sealed with the stiffener and the conductive adhesive layer, and a solder ball is fixed to the bump.
According to a third aspect of the present invention, there is provided a method for manufacturing a package for accommodating electronic parts, comprising the steps of: adhering a buildup substrate having a power source and/or a ground layer formed on a core substrate, and signal lines formed on a buildup interconnecting layer to a stiffener with a conductive adhesive layer using a conductive adhesive; and forming a grounding plane using the stiffener and the buildup substrate.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.